Conference: Circuit architecture and design for energy-efficient image sensors

Circuit architecture and design for energy-efficient image sensors, Dr. Sc. Abdel Martínez Alonso, Japan. Proposal for a conference which will take place in the sessions of 9th International Symposium on Electronics, Automation and Robotics: design, applications, advanced techniques and current challenges, at the International Convention and Fair Informática 2024.

Information will be provided on the latest advances in image sensor architecture design, conversion techniques and frequency generation. The first part will explore architecture and circuit design for energy efficient image sensors; the focus is on the single-slope column analog-to-digital converter (SSADC) for CMOS image sensors (CIS). In the second part, the design of a Phase-Locked-Loop (PLL) loop for image sensors will be discussed in depth; a multiphase Gray-coded PLL at 648 MHz, implemented in 180 nm CMOS technology, will be presented.

The purpose of the 9th International Symposium on Electronics, Automation and Robotics is to create an appropriate environment to stimulate the exchange and renewal of ideas and knowledge, to present the latest scientific and technological advances and to broaden the horizon of their applications and contributions to society. In order to achieve this goal, face-to-face and virtual modalities will be held and combined in a single event.