Circuit architecture and design for energy-efficient image sensors
: 21 de March de 2024
: 10:45 am
: Palace of Conventions – Room 7
Abstract:
Information will be provided on the latest advances in image sensor architecture design, conversion techniques and frequency generation. The first part will explore architecture and circuit design for energy efficient image sensors; the focus is on the single-slope column analog-to-digital converter (SSADC) for CMOS image sensors (CIS). In the second part, the design of a Phase-Locked-Loop (PLL) loop for image sensors will be discussed in depth; a multiphase Gray-coded PLL at 648 MHz, implemented in 180 nm CMOS technology, will be presented.
